In the static logic OR arrays of prior art programmed logic arrays (PLA's) such as shown in FIG. 2 of U.S. Pat. No. 3,566,153, the sources of OR array input devices Q11 through Qmk are connected to ground reference potential. In order to provide reasonably fast voltage rise time at the drains of all of the input devices which are connected together at Sp1, Sp2, etc. and have large parasitic capacitance, the resistive load 15 must have low impedance. When the resistive load has low impedance, all of the array input devices must be fabricated with wide channel areas so that even lower resistance is provided by an input device Qmk in order to reliably turn off the next circuit stage device when desired. Thus, large silicon areas and high currents are consummed.
Another patent showing the same general configuration but with differing voltage polarities and source drain connections is U.S. Pat. No. 3,816,725. The circuit arrangement of this patent also consumes relatively large chip areas and power.
It is known that the use of phase clock switched load resistances decreases power consumption. FIG. 1 of U.S. Pat. No. 3,601,627 is an example of general purpose dynamic logic circuit having switched charging and discharging devices 1 and 14 respectively. FIG. 2 of U.S. Pat. No. 3,974,366 shows an application of switched load resistances to programmable logic arrays. A complete explanation of a PLA designed using clocked phase controlled resistances, also called dynamic logic circuits, is shown particularly in FIG. 2 of "High Speed Dynamic Programmable Logic Array Chip" by R. S. Wood, in IBM Journal of Research and Development, Vol. 19, No. 4, July 1975 beginning at page 379. Although the power dissipation of the dynamic logic circuits of U.S. Pat. No. 3,974,366 is somewhat improved, a significant time delay is introduced by the need to prevent invalid signals generated during precharging of the AND array output lines 111, 131 from energizing OR array input devices 24, 25, 26 while the OR array output nodes 211, 231 are being precharged. This external clocking can be provided between arrays by blocks 3 and 4 as shown in U.S. Pat. No. 3,974,366, but such placement between arrays complicates design of multiple AND array PLA configurations such as taught in FIG. 3 of U.S. Pat. No. 3,975,623.
Another example prior art teaching is U.S. Pat. No. 3,678,293. This patent shows devices L4 and Q4 which provide reliable switching of device Q3 by raising its source potential to compensate for voltage drops across diffusion and other distributed impedances designated as R1. There is no teaching directed to reduction of current through Q3 or reduction of the size of Q3. This patent is a good example of an alternate embodiment for inverter devices 41 and 42 of FIG. 1 in the instant specification.